Double Data Rate (DDR) Dynamic Random Access Memory (DRAM) generally needs to be trained before it may be utilized. For example, hardware registers are typically programmed with values to cause delays so that commands and data may be sent and received when expected. In DDR3 memory, this calibration may be performed on a per lane basis, because the commands and data may propagate to each DRAM component in a memory module at a different time. For instance, a DDR DRAM interface may include two signal classes, DQ for data and a DQS data strobe. During a read operation, the DDR DRAM may issue these two signal classes at the same time, e.g., as edge aligned signals. Then, to correctly acquire data sent from the DDR DRAM, a DRAM controller may utilize a Delay-Locked Loop (DLL) circuit to delay the DQS signal so that it may correctly latch the DQ signals. Similarly, the DRAM controller may also utilize DLL circuits to support writing data to the DDR DRAM. However, topological and electrical differences between DQ and DQS interconnections can make it difficult to determine appropriate delays for the DLL.
Timing delays provided by DLL circuits may often be customized for a particular design configuration, such as by utilizing a training program stored in a Basic Input/Output System (BIOS) memory device and/or implemented within device hardware/firmware. The training program may execute an algorithm to determine appropriate timing delays associated with various memory interface signals. An algorithm for training a DDR3 memory may often be required to execute on a variety of circuit boards and memory combinations. Variances may be present in these different configurations that are difficult for a single set of algorithms to account for. For example, an algorithm may be required to find a certain point of a DQS strobe signal and indicate a hardware delay to inform a training entity (e.g., firmware) of a characteristic of the DQS signal at that point. If the algorithm fails to find the necessary delay, the DDR training may not be able to continue, and the DDR memory may be unusable. Complications in finding the desired point of the DQS signal may include jitter, the signal being tri-stated at times, and other factors that may cause the strobe signal to look different than expected.